In general, semiconductor memory devices are manufactured by depositing thin films for several functions on a wafer surface, patterning it, and forming the geometrical structure of various circuits. Unit processes to manufacture such semiconductor devices may be largely classified as several unit processes, such as: wafer and chamber cleaning processes, etc. to eliminate impurity, including an impurity ion implantation process of implanting impurity ions of group 3B, i.e., B, or group 5B, i.e., P or As, into the interior of semiconductor; a thin film deposition process of forming a material film on a semiconductor substrate; an etching process of forming a given pattern for the material film; an etching process of forming the material layer in a given pattern; and a planarization process (CMP: Chemical Mechanical Polishing) of depositing an interlayer insulation film etc. on the wafer and then collectively polishing the wafer surface to remove a step coverage.
Communication devices and computers are now requiring semiconductor memory devices to have high operational speeds and relatively large storage capabilities. Thus, semiconductor memory devices are increasing in integration level; meanwhile, the design rule becomes reduced. In manufacturing semiconductor memory devices by using such several unit processes, step coverage of the material layer may become defective due to step coverage with adjacent patterns, and the resolution level may decrease in a photolithography process and, thus, it may be difficult to obtain a precise profile. Furthermore, owing to the lack of a process margin, a misalignment may be caused and the reliability of semiconductor memory devices may decrease, thereby negatively affecting yield.
Because of such large capacity and higher integrated tendency in current semiconductor memory devices, the size of respective unit devices constituting memory cells are miniaturized and a process margin is also reduced. This brings about a remarkable development in a high integration technology forming a multilayer structure in a limited area. As an example of the high integration technology for such a multilayer structure, for example, a double layer process of coupling plural metal layers through a metal via contact or a stack transistor process of forming two or more transistors in a vertical structure on the same vertical line of the semiconductor substrate are used generally. For example, in an SRAM, power consumption is less as compared with other memories, but the speed is very fast, thus the SRAM is widely used as cache memories etc. of large capacity and high performance computers, but six transistors constitute one cell structure and thus there is a disadvantage in view of the integration as compared with other memories. Thus the double layer process and the stack transistor structure obtained by vertically stacking at least two layers of transistors, etc. are widely used.
As described above, in employing the double layer process or stack transistor structure etc. to adapt the semiconductor memory devices to the tendency of high integration and in realizing such high integration technology, relatively high precision may be required in unit processes.
For example, in several unit processes applied to the manufacture of semiconductor memory devices, an etching process is one of main processes to form the pattern of material layer for several functions on an upper surface of wafer. In such etching process, among an overall material layer deposited on a semiconductor substrate, only a necessary portion remains and an unnecessary portion is removed. The etching process may be largely classified as wet etching and dry etching. The wet etching is to perform a patterning of material layer by using liquid chemical material, and the dry etching is to pattern a material layer by using gas plasma or ion beam or sputtering without using liquid chemical material. However, as the high integration of semiconductor devices becomes accelerated, a step coverage between respective unit areas constituting a memory cell increases and so an aspect ratio increases, and a line width of circuit patterns becomes more detailed so as to match to such high integration of semiconductor devices, therefore the dry etching is widely used for a more precise pattern.
In such dry etching, particularly in a photo etching process of transferring a pattern of reticle (mask) onto a wafer, there are steps of covering an entire upper part of wafer with photoresist, applying heat and baking to maintain the evenness of the photoresist covering the entire upper part of wafer, partially exposing the photoresist of a portion corresponding to a pattern formed in the reticle (mask) by irradiating light such as ultraviolet rays etc., performing a developing by spraying developing solution to wafer completed in the exposure and thus removing a portion having the irradiation of light or portion not having the irradiation of light in the exposure process through a chemical reaction, and measuring a developed state and aligned state and checking a defect.
In particular, in the checking step it is clarified whether a position alignment between pattern formed through a previous photo etching process and pattern formed through a current photo etching process has been well performed, by using an overlay measurement device. The reason of definitely clarifying such overlay level between the pattern already formed in the previous step and the pattern to be newly formed in the current step is that such overlay level between a lower layer and an upper layer becomes an important factor of deciding a yield and reliability of semiconductor memory devices according to the high integration and miniaturization of semiconductor memory devices. Such overlay between lower layer and upper layer is generally measured through an overlay mark constructed of a main scale and a subscale, and such overlay mark is mainly formed in a scribe area so as not to influence a memory cell area.
Further, in the checking step, together with the overlay confirming operation described above it is checked and confirmed whether a width of pattern transcribed in the wafer was formed as a desired size, by using a critical dimension scanning electronic beam microscope (CDSEM). However, the number of CD (Critical Dimension) measurement points to be tested per step of process is getting increased by an increased integration in a semiconductor chip manufacturing process, thus an Auto CDSEM system is actively used.
Further, there has been recently introduced a metrology automation system for performing a global matching between a graphic data system (GDS) image and a CD (Critical Dimension) scanning electron microscope (SEM) image of measurement position by interlocking a CDSEM and GDS image as a storage format of layout, thereby measuring a number of measurement points through one recipe write. However a matching rate between patterns reaches only 90% due to an incompletion of matching algorithm between a GDS image and an image from the CDSEM, thus a point that matching fail has occurred is compensated through a correction of recipe.
FIGS. 1A and 1B illustrate a GDS image in an FOV (Field Of View) having an error of pattern matching according to conventional art.
FIGS. 1A and 1B illustrate a GDS image for a pattern 12 formed on a lower material layer 10. A position 14 of a target is designated on a center portion of the GDS image. In FIGS. 1A and 1B, a pattern matching error position is shown and it is found that the pattern matching error has occurred in an X direction in the event of pattern matching. In this case, when moving an integer multiple of repeated pitch, it is decided as the same image and then an image is shifted right and left to compare. During such comparison operation, a pattern matching is stopped at a position that is decided as any more similar position. That is, positions of satisfying the condition of pattern matching may become several.
FIGS. 2A and 2B illustrate a GDS image of a FOV with a successful pattern matching.
FIGS. 2A and 2B illustrate a GDS image for pattern 22 formed on lower material layer 20. A position 24 of target is indicated in a center portion of the GDS image. In FIGS. 2A and 2B, an exact pattern matching state is shown without indicating the pattern matching error position 16. This is a unique image without a pattern repetition in right and left and upward and downward, and a position satisfying a pattern matching condition is one.
An analysis for a corresponding image to get a satisfied pattern matching method can provide the following result.
a) A pattern matching error occurrence image has a repeated pattern of a specific direction and a specific pitch.
b) A shifted level in a pattern matching error occurrence is an integer multiple of pitch.
c) An image succeeded in a pattern matching is not repeated in the pattern.
As shown in FIGS. 1A and 1B, causes why a GDS image 14 within FOV does not accord with a CDSEM image for an actual pattern may be as the following description.
Image for pattern existing in the FOV area is obtained by measuring a measurement point through CDSEM, and then a pattern matching with the GDS image is performed. When in the pattern matching with the GDS image, an image is repeated in Y and X directions and the measurement is performed for a movement of distance corresponding to an integer multiple of repeated pitch, the pattern matching is performed at a faulty position.
Like that, for example, when a global matching between GDS image and CD SEM image is not normally performed, a measurement fail occurs and so a CD value of undesired position is measured, thus the reliability of a measurement value falls, causing a failure in a process monitoring step using such a measurement value.
Further, when the global matching between the GDS image and the CDSEM image is not normally performed, there is an inconvenience to have to review a number of measurement points and to have to re-measure relating to a matching fail point, thus causing time consumption and a decrease in a driving rate of metrology system.
However, when a global matching between a GDS design in a FOV and a CDSEM image for an actual pattern is not precise, an alignment of patterns formed in a subsequent process is getting worse, thus largely decreasing reliability and productivity of semiconductor memory devices.